Generally, the semiconductor memory devices, which have NMOS and PMOS transistors, include different circuits to be driven by different voltage levels. Since leakage current occurs when the circuits, which are driven by different voltage levels, are directly connected to each other, a level shifter is employed to prevent such the leakage current in the semiconductor memory devices.
The level shifter converts a low level input signal, which is driven by a low level driving circuit, into a high level output signal and transfers the high level output signal to a high level driving circuit, or converts a high level input signal, which is driven by a high level driving circuit, into a low level output signal and transfers the low level output signal to a low level driving circuit.
FIG. 1 is a circuit diagram illustrating a conventional level shifter.
As shown in FIG. 1, the conventional level shifter includes PMOS transistors P10 and P11 for a current mirror and NMOS transistors N10 and N11 which are selectively turned on in response to an input signal IN.
The operations of the conventional level shifter can be illustrated in the cases where the input signal IN goes from a first voltage level V1 to a ground voltage level VSS and goes from the ground voltage level VSS to the first voltage level V1.
First, when the input signal IN is at the first voltage level V1, the NMOS transistor N10 is turned off and the NMOS transistor N11 is turned on. Accordingly, a node nd11 is pull-down driven to the ground voltage level VSS so that the PMOS transistor P10 is turned on and a node nd10 is pull-up driven to a second voltage level V2. At this time, if the input signal IN goes to the ground voltage level VSS, the node nd10 is pull-down driven to the ground voltage level VSS by the NMOS transistor N10 which is turned on and the node nd11 is pull-up driven to the second voltage level V2 through the turn-on operation of the PMOS transistor P11. When the node nd11 is at the second voltage level V2, an output signal OUT is at the ground voltage level VSS through an inverter IV12.
Next, when the input signal IN is at the ground voltage level VSS, the NMOS transistor N10 is turned on and the NMOS transistor N11 is turned off. Accordingly, the node nd10 is pull-down driven to the ground voltage level VSS so that the PMOS transistor P11 is turned on and the node nd11 is pull-up driven to the second voltage level V2. At this time, if the input signal IN goes to the first voltage level V1, the node nd11 is pull-down driven to the ground voltage level VSS by the NMOS transistor N11 which is turned on. When the node nd11 is at the ground voltage level VSS, the output signal OUT is at the second voltage level V2 through the inverter IV12.
As mentioned above, the level shifter receives the input signal IN, which has a swing width between the first voltage level V1 and the ground voltage level VSS, and then outputs the output signal OUT which has a swing width between the second voltage level V2 and the ground voltage level VSS.
However, in the conventional level shifter, there is a delay section at the time of the pull-down operation to the ground voltage level VSS on the node nd10 because the turn-on states of the NMOS transistor N10 and the PMOS transistor P10 are simultaneously generated and such turn-on states are maintained for a predetermined section when the input signal IN transits from the first voltage level V1 to the ground voltage level VSS. This is a cause of the delay in the generation of the output signal OUT of the ground voltage level VSS. Further, in the conventional level shifter, there is a delay section at the time of the pull-down operation to the ground voltage level VSS on the node nd11 because the turn-on states of the NMOS transistor N11 and the PMOS transistor P11 are simultaneously generated and such turn-on states are maintained for a predetermined section when the input signal IN transits from the ground voltage level VSS to the first voltage level V1. This is a cause of the delay in the generation of the output signal OUT of the second voltage level V2. These causes of the delay are generated even if the voltage difference between the first voltage level V1 of the input signal IN and the second voltage level V2 of the output signal OUT is at a small range.